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Gearing Up for 3D Designs: Just High Tide or a Tsunami?
October 22, 2009

Sumit Dasgupta
Sr. Vice President of Engineering, Si2

There is quite a buzz building around the concept of 3D integration of semiconductor chips to meet the challenge of “More than Moore” which has received considerable attention in recent issues of the International Technology Roadmap for Semiconductors (ITRS). This idea, in reality, is not an entirely new one – memory manufacturers have been doing this for years. But what is new is the challenge of integrating chips, potentially made in different foundries at different process nodes with digital logic, analog circuits, memory and other functions operating at different power levels and frequencies, on vertical stacks with all connected through the use of through-silicon-vias (TSV). Besides the technological challenges associated with this nascent TSV technology, the design of 3D chips requires design processes/flows that include all the complexities of leading-edge 2D chips as well as the need to connect the flow, for instance, to thermal and mechanical stress analyzers. This calls for standardized interfaces to express, model and store the data required to represent the chip stacks and TSV’s to ensure smooth, interoperable design flows.

The Si2-GSA 3D Workshop (formally named as Si2-GSA 3D Workshop on Requirements for 3D Design Flow Interoperability Standards) was held at the Santa Clara Convention Center on Thursday, October 1, 2009. The goal was to connect requirements and priorities for standards to enable interoperable deign flows using best-in-class design tools. There were almost 50 attendees from over 35 companies representing all stakeholders from the semiconductor industry - systems, IDM's, memory, fabless, EDA, IP and foundry companies - as well as members from academia and other standards organizations. The workshop attendees heard presentations from representatives from all the stakeholder segments of the semiconductor industry to ensure a common understanding of the challenges. All of these presentations are posted on Si2’s web-site (http://www.si2.org/?page=1084) and soon will also be posted on GSA’s web-site.

A treasure trove of information and requirements was collected to define areas where standards would greatly facilitate (or enhance) 3D chip design. While this information is being compiled and assimilated at the present time, a quick summary, though not complete by any means, of standardization activities include the following:

  1. Creation of a standard dictionary of terms to ensure clear communication among all involved in 3D design
  2. Interfaces, languages, etc to express, model, and analyze TSV’s in a design
  3. Enhancements to the design tool infrastructure to design 3D chips including API’s, databases, languages, etc
  4. Interfaces to thermal/mechanical stress analyzers
  5. Enhancements to DFT and test method standards for 3D designs

The most important message drawn from this workshop is that modeling of through-silicon-vias (TSV's) is a significant challenge and that 3D design will not only require significant enhancements to existing design flows and tools for 2D design but will require new methods for design exploration and implementation across a third dimension as well as methods to access analysis tools for mechanical and thermal stress. The requirements gathered at the workshop will form the basis for future work on standards development activities at Si2 and other partner organizations.

For further information, please contact Sumit DasGupta if you wish to know more about this workshop or to join in any new standards effort at Si2.




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