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DFMC Workshop

Design for Manufacturability Coalition Workshop
Date:     Sunday, June 13
Time:     1pm-4pm
Meeting room:    207C

Free Admission, Register at DAC Website

The workshop will educate the audience on a high level DFM verification and optimization language called OpenDFM. OpenDFM rules bridge the gap between a layout style that allows only a few, very restricted layout patterns and a style that allows purely arbitrary layouts. OpenDFM functions transform database shapes, regardless of their origin and design style, into the on-silicon target shapes that design and manufacturing both agree are the reference shapes for silicon based measurements and extraction. OpenDFM increases the level of pattern uniformity in the layout and it polishes the rough spots in the layout when it finds layout patterns that are known to be problematic. OpenDFM modifies the design to physically optimize and measurably affect electrical performance to enhance Process Limited Yield (PLY) and/or Circuit Limited Yield (CLY) during the design process and not at post tapeout.

This workshop is not intended to continue to admire the problems of Design for Manufacturing for SoC design but to show that real progress is being made. As part of the workshop, selected vendors will present their products aimed at helping designers produce higher yielding integrated circuits and systems.

Luigi Capodieci - GLOBALFOUNDRIES, Sunnyvale, CA
Rhett Davis - N. Carolina State Univ., Raleigh, NC
Bob Pack - Grid Simulation Technology, Inc., Morgan Hill, CA
Wilbur Luo - Cadence Design Systems, Inc., San Jose, CA
Qi-De Qian - IC Scope Research, Santa Clara, CA

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