Login Register Now
       
       
Site Map   
Production Standards Open Standards

  Features
features 1

Current Feature Downloads List

The Si2 Enhanced Standards Development Process 2016
Incubation and Development stages are used to identify, write, prove-out and approve new standards for industry adoption or contribution to a standards development organization. Production standards include quality-assured code used across the industry. (Effective January 1, 2016)

A Perspective On Open Process Specification by Ted Paone
It is the job of the Process Design Kit (PDK) engineers to deliver a high-quality PDK that properly represents the process requirements and constraints and supports the design flows used by their customers. The PDK engineer takes multiple inputs describing the process and the devices and circuitry in the process and output in the form of OpenAccess technology libraries (techDB), design parameter definitions, pcells, verification decks, models and other code which describe the process to the design tools in the flow. To the end user, the resulting PDK should operate seamlessly within their chosen flow. To that end, the PDK engineers must thoroughly test the pcells and PDK to make sure it models the process accurately.

read more ....

Compact Model Council Moves to Si2: Video
On Video, Dr. Keith Green the chairman of the Compact Model Council describes the move of the Council to Si2 where it is now known as the Compact Model Coalition.

Compact Model Coalition Accomplishments
Since the establishment of the CMC in 1996, standard models from the CMC have become widely used around the world. This is the result of a collaborative effort between industry and academia. Each of the CMC\'s transistor models is supported by a university researcher, in most case the person who developed the model in the first place. The CMC provides input to the developer on what areas of development would be of most value to the industry, data from real world devices to enable the development and testing and debug of the models.

Additionally, the CMC developed guidelines for extracting well-proximity effect model instance parameters and a test suite for verifying the accuracy of Verilog-A implementations in circuit simulators.

Compact Model Coalition Open Standards
This list of standard models accomplished by the Compact Model Coalition (prior to June 2012 the Compact Model Council).

Included are download links to well known models:
  • Bulk MOS FET models
  • SOI and Multigate MOS FET models
  • High-Voltage MOS FET model
  • Bipolar Transistor models


Si2 3D-IC Design Exchange Format Standard for Power Distribution Networks
Si2 3D-IC Design Exchange Format Standard for Power Distribution Networks: Si2 Chip Package Interface Protocol V1.0 was published May 30, 2013 by the Open3d Tab.

The 3D-IC Design Exchange Format Standard for Power Distribution Networks (PDN) describes a unified interface protocol for both Power/Ground and signal ports for die-2-die, die-2-package and package-2-PCB interfaces. This also allows the creation of compact SPICE-level descriptions to aid in the design, analysis and optimization of the resulting networks that define these nterfaces to ensure they meet the requirements for power and signal integrity.

Open3DTab 3D Interconnect Architectures Glossary
The Open3DTab 3D Interconnect Architectures Glossary version 1.0 was published 24 October 2012.

From the introduction:

In order to come to a clear vision on roadmaps for 3D technologies, it is important to come to a clear definition
of what is understood by 3D interconnect technology and to propose a classification of the wide variety of
technologies. This definition should capture the functional requirements of 3D technology at the different
hierarchical levels of the system and correspond to the supply chain manufacturing capabilities.

ESD Protection Design Methodology Standardization Proposal V1.0
The design of ESD (Electro-Static Discharge) protection devices in an integrated circuit should be evaluated and verified at all stages of a standard circuit design flow starting from the Cell Schematic level and ending at the Full Chip Layout level. A comprehensive set of ESD checks should be verified using appropriate tools at each of these levels to ensure that the integrated circuit has robust ESD protection. In this paper, we describe the ESD design flow, the various checking tools that are used at each level and the requirements for each of these tools.

This document, published December 2012, is the work of the OpenPDK Coalition Electrostatic Discharge (ESD) Working Group.

Si2 oaDebugging Suite
The Si2 oaDebugging Suite is a single binary release per OS. It includes all of the Si2 OpenAccess debugging tools in one package.

  • Si2oaD displays oaObjects from a persistent repository or run-time model (RTM) along with their attribute values and relationships to other Objects.

    Both batch (XML format) and GUI (browser) modes support filtering options. The GUI (active HTML) mode enables dynamic relationship traversal, incremental data loading, and on-demand binding across by-name associations.


  • Si2Dff compares two designs and outputs the differences in a method selected by the user. Si2oaForensics helps debug environment issues related to running OA.

Over the years Si2oaD has been called: Si2oaDebug, oaDebug, and simply, OAD.

Universal Layer Model V1.0
Jointly developed by the DFM and OPDK coalitions,the Unified Layer Model (ULM) attempts to standardize the data model for both drawn layers and derived layers. The ULM standard is a specification that standardizes the layer operators and guarantees the expected results from ULM layer operations.

Si2 2014 Member Report
The Si2 2012 Member Report summarizes the year\'s accomplishments by Si2 initiatives including:

  • OpenAccess Coalition (OAC)
  • Design for Manufacturability Coalition (DFMC)
  • Low Power Coalition (LPC)
  • OpenPDK Coalition (OPDKC)
  • Open3D TAB
  • Silicon Photonics TAB (SPTAB)
  • and CMC


Lef/Def Exchange Format Version 5.8 2012-12-20
The Lef/Def Exchange Format Version 5.8 includes the Lef/Def 5.8 specification plus LEF/DEF reader/writer source.

OpenPDK Design Parameter & Callback Specification V1.0 2012-05-24
This initial release contains

  • A document that helps to explain:
    • The data used to define parameters
    • The semantics of specifying callbacks

  • An XSD (Xml Schema Definition) file, which is the normative specification for the parameter data
  • A tar.gz containing xml examples that will parse against the xsd.

    These examples are not meant to be realistic and are for format
    illustration only.

3D Interconnect Architectures Glossary V1.0 24-Oct-2012
In order to come to a clear vision on roadmaps for 3D technologies, it is important to come to a clear definition
of what is understood by 3D interconnect technology and to propose a classification of the wide variety of
technologies. This definition should capture the functional requirements of 3D technology at the different
hierarchical levels of the system and correspond to the supply chain manufacturing capabilities.

OPDKC OPS 1.2
The OPDKC Open Process Specification (OPS) is targeted at Process producing companies (Foundries), to enable
study and creation of electronic versions of DRM, to gather early feed-back on completeness.

OPS 1.2 features support the creation of a techfile/oaTech.db for foundry specific layer information. display information, grids, connectivity, and version information.

This release also integrates the Device Parameters (previously called Design Parameters) and Tool Interface standards into OPS.

Cadence Multi Pattern Technology - OpenAccess Extensions 2012-11-09
This Cadence contribution includes OpenAccess extensions which enable physical design tools to represent MPT information. The extensions support assigning mask "colors" to shapes and vias. To enable different instances of a design to be colored differently, the color of the shapes in an oaInst can be shifted on a per-layer basis. The extensions are for use with oa22.43 or later. Downloads require a user account.

oaScript Extension Language Bindings for OpenAccess
The oaScript Work Group continues work on the new OpenAccess extension bindings for the scripting languages: Tcl, Ruby,Perl and Python.
  • Latest releases include binaries for multiple versions of the scripting languages, each built with several recent releases of OpenAccess including oa22.43, oa22.50.

  • OpenAccess Coalition members have access to the latest releases.

  • Si2 Members, who are not OAC members, can also download and use recent releases after obtaining a free license key from Si2.


Value of Si2 and Consortia, Mark Mason, TI
Wonderful insights into the value of consortia and Si2 in particular by Mark Mason of TI. (Flash presentation)

Nangate FreePDK45 Generic Open Cell Library
The Nangate Open Cell Library is a generic open-source, standard-cell library provided for the purposes of research, testing, and exploring EDA flows. This library is purposely non-manufacturable.

Common Power Format (CPF) Version 2.0
The Common Power Format (CPF) Version 2.0 incorporates major enhancements to the widely adopted low-power intent format. Guided by the Si2 Interoperability Guide for Power Format Standards of 2010, CPF 2.0 includes features to improve interoperability with IEEE 1801-2009.


OpenDFM 2.0.1 Physical Verification Specification
The work of the DFMC, Version 2.0.1 expands the OpenDFM 1.1 specification. OpenDFM is an open, high-level DRC language that can generate popular verification languages with no loss of accuracy or performance.


Developing Vision for RLC Parasitics Framework in OpenAccess by Martin Foltin, HP
Martin Foltin\'s presentation from the Si2/OpenAccess+ Congference walks through the possibilities for an RLC Parasisitics Framework in OpenAccess.

Si2 High Level Power Modeling Requirements
Produced by the LPC Modeling Work Group, the Si2 High Level Power Modeling Requirements specification contains requirements for accurately and efficiently describing the power behavior of arbitrarily complex functions and is organized with one section for each independent requirement. Version 1.3 May 30 2012 is available. (Download requires a login)

Si2 Interoperability Guide for Power Format Standards
The guide documents a mapping between the subset of commands and arguments in 1801 and CPF that can be used to describe a low power design with consistent semantics to drive verification and implementation.

Statistical Methods For Semiconductor Chip Design
Developed by the Si2 Open Modeling Coalition
Statistical Working Group, this document addresses the
need, and intended usage, for statistical technics in design flows.

CPF 2.0, 1.1 and 1.0 Tutorials
In depth reviews of the versions of the CPF Standard.

OpenAccess Enables IBM Processor Design Success
Keith Barkley, of the Advanced Processor Design Systems and Technology Group at IBM, outlines the contribution of OpenAccess to their success.

Liberty Extensions for Characterisation and Validation V1.0 Specification
Additional information recommended by the OMC for Liberty in order to establish a characterization environment, to validate models, and to correlate library models against SPICE simulation.(A user account is needed for download.)

Low Power Glossary 1.1
This collection of definitions has been produced by the LPC to enhance communication related to power-aware design and to promote industry-wide standardization. (Login is not required for this download.)

IEEE 1801 Isolation Location Discussion
Discussion of the isolation location from IEEE 1801.(Login is not required for this download.)

DFM Dictionary
The DFM Dictionary will cover the major factors for Process Limited Yield (PLY) which is the product of multiple yield limiters and the Circuit Limited Yield (CLY) which is the result of the widening variability of circuit parameters. (Login is not required for view.)

OpenAccess Tutorial and Labs
The OpenAccess API Tutorial, written by the Si2 staff, is 800+ pages and over 30 labs designed to teach a user the OpenAccess 2.2 API. (A user account is needed for downloads.)

Si2 Power Reduction Stimulus V1.0
Generated by the Low Power Coalition Format Working Group, the objective of this document is to identify and list all low power technologies used in minimizing power consumption in silicon and systems.(Login is not required for this download.)

CPF Parsers for versions 1.0. 1.1 and 2.0
This TCL-based parser is expected to allow CPF users to bring products to market more quickly that support CPF. (Requires an account and an easily submitted license.)

Si2 Power Closure Flow V1.0
Power Aware Flows and Design Techniques compiled by the Low Power Coalition Flow Work Group. (Login is not required for download)

 
Copyright © 2004-2017
Silicon Integration Initiative, Inc (Si2)
All rights reserved
Site Map
How to Get an Account
Contact Si2
Contact Site Admin
Legal Notice/Disclaimer