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By: Bob Carver
RE: How to model a hard macro with pins at different power domains [ reply ]  
2008-05-09 10:30
I am not sure exactly what the problem you are encountering in CLE is. The hierarchical concept is currently being extended for the next release if CPF 1.1. In looking at you example you might want to try creating the power domain PD3V at the same scope as the other two power domains. If you do tat you will need to remove the set_instance command. You will also need to remove the "I_analog." path component from the commands.

By: Daniel S. Borg
How to model a hard macro with pins at different power domains [ reply ]  
2008-05-05 17:21
Can someone please post an example of how to correctly write a CPF file that models an IP block with boundary pins that differ from the instance's power domain?

E.g. suppose there are both a 2V and a 3V domain on the chip.
The 2V domain is the default domain and the 3V is the always-on domain. At the top-level hierarchy, there is an analog hard macro that defaults to the 2V domain. Suppose that some ports of the analog block belong to the 3V domain and the remaining ones belong to the 2V domain.

In my attempt to write a CPF file, I have defined two files:

create_power_domain -name PD2V -shutoff_condition {I_dig_top.I_always_on_block.disable_vdd} -default

create_power_domain -name PD3V -instances {I_dig_top.I_always_on_block}

set_instance I_analog
source analog.cpf

create_nominal_condition -name p2v -voltage 2.0
create_nominal_condition -name p3v -voltage 3.0
create_nominal_condition -name off -voltage 0.0

create_power_mode -name PMALLON -domain_conditions {\
I_analog.PD3V@p3v \
PD2V@p2v \
PD3V@p3v \

create_power_mode -name PM2VOFF -domain_conditions {\
I_analog.PD3V@p3v \
PD2V@off \
PD3V@p3v \

## Isolation cell rule, 2V dig to 3V dig, placed in 3V dig
## Exclude analog ports at 3V level
create_isolation_rule -name iso_l2h \
-from PD2V \
-to PD3V \
-isolation_condition {I_dig_top.I_always_on_block.disable_vdd} \
-isolation_target from \
-isolation_output low \
-exclude {I_analog.port_a_on_3v port_b_on_3v}

create_level_shifter_rule -name lvl_l2h \
-from PD2V \
-to PD3V \
-exclude {I_analog.port_a_on_3v port_b_on_3v}

## Levelshifter Rules lvl_ana from 2V -> 3V analog, placed in 2V
create_level_shifter_rule -name lvl_l2h_ana -from PD2V -to {I_analog.PD3V}

create_level_shifter_rule -name lvl_h2l \
-from PD3V \
-to PD2V \
-exclude {I_analog.port_a_on_3v port_b_on_3v}

create_level_shifter_rule -name lvl_h2l_ana \
-from {I_analog.PD3V} \
-to PD2V


set_design analog
create_power_domain -name PD3V -boundary_ports {port_a_on_3v port_b_on_3v}


The problem with the above method is that the 3V pins of the analog block are not recognized as 3V pins by the CLP verification tool. These pins are still considered as 2V pins and thus my design fails in the verification.


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