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Low Power Workshop DesignCon, Feb. 2-4, 2009, Santa Clara Convention Center, Santa Clara, CA

Low Power Flows and Formats, From ESL to Implementation
Monday, February 2 | 1:30 pm – 4:30 pm, Room 203

Green technologies, including low power design, have been identified as critical areas for design flow improvement in IC and system design. This three hour workshop is intended to review the progress made to date in the areas of low power design formats and to expose and acknowledge the challenges remaining for full interoperability between those formats. Detailed presentations on advances in low power design understanding will be made at the workshop and specific areas of interoperability that remain will be addressed. Advances in Power Aware design flows and Low power design techniques will be presented and supporting documents and technologies will be made available. The workshop will conclude with a panel discussion on “What does interoperability mean?”. The goal of the workshop is to enhance industry understanding of the state of low power design capabilities today and the remaining challenges to full interoperability of low power design flows that will need to be addressed.

01:30PM - 01:45PM: Introduction, Resources, Agenda: Nick English, Si2
01:45PM - 02:15PM: CPF 1.1 Summary and CPF 1.2 Roadmap: Qi Wang, Cadence
02:15PM - 02:45PM: Power Aware Flows and Design Techniques: Jerry Frenkil, Sequence Design
02:45PM - 03:00PM: Break
03:00PM - 03:30PM: P1801 Update: Gary Delp, LSI
03:30M - 04:00PM: Atrenta's Experience with multiple Formats: Dave Allen, Atrenta
04:00PM - 04:30PM  Panel: What does interoperability mean to you? (Above speakers, as well as Dale Pollek, Atrenta)

Panel Cadence
Panel Atrenta
Panel Sequence
Panel LSI
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