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OPDKC Introduction

OpenPDK Coalition Introduction

The OpenPDK Coalition was founded in mid-2010 with the goal of defining a set of open standards to allow an OpenPDK to be created once and then translated into specific EDA vendor tools and specific foundry formats. This will allow an OpenPDK to be as portable across foundries and as agnostic to EDA tools as possible. The Si2 OpenPDK standard will enable greater efficiency in PDK development, verification, and delivery. It will provide equivalent support to all stakeholders: foundries, EDA tool vendors, IP providers, and end-users.

Open Process Specification (OPS) version1.1 will be delivered in late 2013. This will extend the Open Process Specification with connectivity below metal 1 to allow full Layout vs. Schematic (LVS)capability and allow EDA vendors to start building tools compatible with the specification.

A Pcell Working Group was formed in early 2013 to work on the concept of a pcell language that supports a “write once and use many” approach. This is increasingly important as more design kits are being produced by fewer experienced developers for multiple EDA platfoms. The key requirement of a common coding language is to define a grammar based on an existing language that can be translated into the major pcell and callback languages already in use in the industry without requiring API’s not owned and supported by the OpenPDK initiative. The requirement supports innovation by allowing embeddable proprietary code and alternative implementations.

A translator to convert the Open Process Specification (OPS) to the OpenAccess Technology Database will be delivered in 2013. This will be a basic translator that will be an example of how to move the XML data described in OPS to the binary OpenAccess incremental technology database. It is planned to be extensible so that EDA vendors and user companies may take the example and extend it for their own needs.

ESD Protection Design Methodology Specification V1.0 was published in 2013, The design of ESD (Electro-Static Discharge) protection devices in an integrated circuit should be evaluated and verified at all stages of a standard circuit design flow starting from the Cell Schematic level and ending at the full chip layout level. A comprehensive set of ESD checks should be verified using appropriate tools at each of these levels to ensure that the integrated circuit has robust ESD protection. This Methodology document should be of value to the EDA and semiconductor industries and Si2 has made this document available to the entire community.

A standard Tool Interface Specification was published in 2013. An example of a commonly adopted format among EDA vendors is an ASCII netlist representing a hierarchical description of wires and their connections. However, this description can vary according to the target application
that reads a netlist. Each target application expects the circuit description in a certain format that suits its needs. It is the responsibility of the netlister tool to generate the output description of the design in a structure and a format that is acceptable to the target application. Tool interfaces describe how process design kit components are presented to a target netlister. This standard tool interface specification will allow
all companies to present information in a standard manner to a variety of applications.


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